1. Field
Example embodiments relate to a memory device and a method of operating the memory device, for example, to a memory device and a method of operating a memory device for reducing a lateral movement of charges, which may be caused by an electrostatic attraction force of the charges stored in memory cells of the memory device, so as to preserve information for a longer period of time.
2. Description of the Related Art
Among semiconductor memory devices, non-volatile memory devices may preserve data even when a power supply to the non-volatile memory devices is stopped.
Floating gate-type flash memories, which may operate by storing charges in a floating gate formed of polycrystalline silicon, may be used as non-volatile memories with large storage capacities.
Memory cells of a flash memory device may be classified into a single-level cell (SLC) recording two levels of a recording state (1 and 0) therein and a multi-level cell (MLC) recording four or more levels of a recording state (for example, 11, 01, 00, and 10) therein.
The MLC technology may increase the storage capacities of NAND type flash memories and NOR type flash memories.
In operating the MLC, the distribution of threshold voltages Vth corresponding to the recording states may be reduced so that each of the recording states may be separately recognized.
In the flash memory that uses the floating gate, when the sizes of the memory cells are reduced, it may be difficult to control the distribution of the threshold voltages Vth due to an increase in a coupling between the memory cells, for example, the coupling between the floating gates of the memory cells.
To solve the above problem, charge trap flash (CTF) memory devices that include an insulating layer having a charge trap site are using a charge trap layer, such as silicon nitride (Si3N4), as a charge storage layer instead of using the floating gate.
In CTF memory devices, since the charges are trapped in the insulating layer having the charge trap site such as the silicon nitride Si3N4, the trapped charges may move between charge trap sites of the insulating layer by tunneling or hopping, when the electrostatic force between the charges stored in adjacent memory cells strengthens.
In programming the CTF memory device, a voltage of 0V may be applied to an active region corresponding to a selected bit line, and a power voltage Vcc may be applied to unselected bit lines. At a same time, a programming voltage Vpgm may be applied to selected word lines and a pass voltage Vpass may be applied to unselected word lines. Due to the above programming, electrons may be injected into the memory cell, on which the selected bit line and the selected word line overlap each other, through a tunneling oxide layer. The injected electrons may be trapped and stored by charge trap sites that are scattered in the charge trap layer.
When programming the MLC, an incremental step pulse programming (ISPP) method may perform the programming while repeatedly boosting the programming voltage Vpgm by a predetermined value in order to reduce the distribution of the threshold voltages Vth of the memory cells respectively corresponding to levels of the programmed state.
On the other hand, when data stored in the CTF memory device is erased, an erasing voltage Vers may be applied to a bulk portion and the voltage of 0V may be applied to all of the word lines so as to erase the data in a block unit. Here, in the memory device, a block may include a plurality of pages, and a page may be defined as the memory cells connecting to one word line when a plurality of memory cells that are connected to a bit line in series form a string in a NAND type flash memory device. The reading operation and the programming operation may be performed in a page unit, and the erasing operation may be performed in the block unit.
When the erasing operation is performed, holes may be injected into the charge trap layer from the active region through the tunneling oxide layer, to neutralize and erase the electrons stored in the memory cells in the programming operation.
Since the data may be erased from all of the memory cells included in a block, the threshold voltages Vth in the erasing operation may be highly scattered and the distribution of the threshold voltages Vth may not be controlled, unlike in the programming operation. Due to the above characteristic, the erasing operation may be sufficiently performed to erase the data from all of the memory cells, and consequently, the distribution of the threshold voltages Vth in the erasing operation may have a negative value of wide range, for example, from 0V to −3V.
On the other hand, since the memory cells in the programmed state have the positive threshold voltages, a difference between the charge potentials of the memory cells in the programmed state and the erased state may be greater. Due to the difference between the charge potentials, the charges stored in the charge trap layer may move in the direction of the word lines.
When the stored charges slowly move in the direction of the word lines after performing the programming operation, the threshold voltages of the memory cells in the programmed state may be reduced gradually, and thus, the stored data may be lost. Therefore, the moving of charges stored in the charge trap layer in the direction of the word lines may degrade a reliability of the CTF memory device.